Memory circuits are often used as buffers to store data for use by multiple processors. In order to prevent erroneous address, data or control signals, and the resultant loss of integrity in the memory data, access to the memory must be controlled is such a manner as to ensure that only one processor has access to the memory at any particular time.
Such memory access control typically requires complex timing, priority and logic circuitry.
A circuit used for controlling access of dual input-output devices to a single controller was disclosed in U.S. Pat. No. 4,314,164 issued Feb. 2, 1982, to S. R. Norman and K. B. Tin. However, this circuit required the use of retriggerable monostable multivibrators and predetermined time slots.
Accordingly, it is the object of the present invention to provide a novel memory access control circuit which does not require the use of time slots or complex timing, priority and logic circuitry.